The present invention relates generally to semiconductor integrated circuits and, more particularly, to applications for non-volatile memory cells.
Many products need various amounts of memory. Two of the most useful types of memory are high speed, low cost memory typically implemented as dynamic random access memory (DRAM) and non-volatile memory typically implemented as electrically erasable and programmable read only memory (EEPROM) or Flash memory.
This invention relates to non-volatile memory cells being used in conjunction with DRAM memory cells. Micron Technology, Inc. taught in U.S. Pat. No. 5,324,681 which issued to Lowrey et al. on Jun. 28, 1994, that one time programmable (OTP) memory cells could be used to replace laser/fuse programmable memory cells for applications such as OTP repair of DRAMs using redundant rows and columns of DRAM memory cells and OTP selection of options on a DRAM (such as fast page mode (FPM) or extended data out (EDO)). One of the key advantages of that capability is the ability to program the OTP memory cells after the DRAM memory chip is packaged (a decided advantage over previous solutions).
The antifuse integrally combines the functions of a switching element which makes the interconnection and a programming element which stores the state of the switching element, either xe2x80x9coffxe2x80x9d or xe2x80x9con.xe2x80x9d Thus an antifuse occupies little space on the integrated circuit, but has the disadvantage of not being reprogrammable. This single-time programmability makes the antifuse difficult to test and unsuitable for a large class of applications where reprogrammability is required.
Alternative programmable interconnects use a metal oxide semiconductor field programmable transistor (MOSFET) as the switching element. The MOSFET is controlled by the stored memory bit of a programming element. Most commonly, this programming element is a dynamic random access memory (DRAM) cell. Such DRAM based FPGAs are reprogrammable, but the programming of the switching elements is lost whenever power is turned off. A separate, non-volatile memory cell must be used to store the programmed pattern on power down, and the FPGA must be reprogrammed each time the device is powered back up.
It is further desirable to implement non-volatile memory cells along with DRAM cells to provided shadow RAM cells. An example of conventional shadow RAM cells is taught in U.S. Pat. No. 5,196,722 issued to Bergendahl et al. on Mar. 23, 1993. However, the process steps involved there are lengthy and do not fit well with an optimized DRAM technology process flow.
The ability to combine DRAM and non-volatile, e.g. EEPROM, styles of memory, especially if little or no additional manufacturing complexity is required, would facilitate a number of cost effective applications, as described above, which do not currently exist or that, heretofore were too costly to be commercially viable.
Thus, there is a need for additional applications for DRAM technology compatible non-volatile memory cells. It is desirable that such DRAM technology non-volatile memory cells be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. It is further desirable that such DRAM technology non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.
The above mentioned problems for merging additional applications for DRAM technology compatible non-volatile memory cells onto the DRAM chip as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. The present invention includes a compact non-volatile memory cell structure formed using a DRAM process technology.
The present invention employs DRAM technology compatible non-volatile memory cells for implementations which dramatically improves on the prior art. An example of one such application includes a circuit switch. The circuit switch has a non-volatile memory cell which has a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to logic/select circuit.
Another example of an application includes a shadow random access memory (RAM) cell. The shadow RAM cell has a non-volatile memory cell with the structure described above. Other implementations of the present invention may similarly be included.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.